Processing technologies and device structures for forming integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors or devices. A well known sub-set of MOS transistors are referred to as laterally diffused metal oxide semiconductor (LDMOS) transistors or devices. Although the term “MOS device” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or not) that is positioned over a gate insulator (whether oxide or other dielectric material) which, in turn, is positioned over a semiconductor surface. Accordingly, the terms metal-oxide-semiconductor and the abbreviation “MOS” are used herein even though such devices may not employ just metals or oxides but combinations of conductive materials, e.g., alloys, silicides, doped semiconductors, etc., instead of simple metals, and insulating materials other than oxides (e.g., nitrides, oxy-nitride mixtures, etc.). Thus, as used hereon the terms MOS and LDMOS are intended to include such variations.
A typical MOS transistor includes a gate electrode as a control electrode and spaced-apart source and drain electrodes between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a controllable conductive channel between the source and drain electrodes. In an LDMOS device, a drift space is provided between the channel region and the drain region. For convenience of description and not intended to be limiting, N-channel LDMOS devices are illustrated herein, but persons of skill in the art will understand that the present invention is not limited merely to N-channel devices and that P-channel and other types of devices may be provided by, for example, substitution of semiconductor regions of opposite conductivity type.
FIG. 1 is a simplified schematic cross-sectional view through LDMOS device 20 according to the prior art. Device 20 is formed in a semiconductor and comprises optional N-type buried layer (NBL) 21 and P-type substrate (P-SUB) 22, in which have been formed N-type drift space or region 24 and P-well 26 having PN junction 25 therebetween, extending to surface 27. N+ drain 28 is formed in N-drift space 24 and N+ source 30 is formed in P-well 26. P+ body and P-well contact region 31 is also typically provided in P-well 26. P-type buried layer (PBL) 23 may also be included but is not essential. Gate dielectric 34, e.g., silicon oxide, is formed on surface 27. Gate 36 is provided on dielectric 34 extending laterally approximately from source 30 to and overlapping N-drift space 24. Intermediately doped N-type diffused region 32 may also be provided extending from source 30 under the edge of gate 36 to insure that a high resistance region does not exist between source 30 and channel 35 in P-well 26 through which flows source-drain current Id. Dielectric side-wall spacers 37 and 38 are provided covering lateral edges 361-362 of gate 36. Sidewall spacer 38 also extends over portion 271 of surface 27 above N-drift space 24 to drain 28. Portion 271 also corresponds to the gate-drain separation distance. Portion 381 of spacer 38 between gate edge 362 and drain region 28 is often referred to as a “silicide blocker” since its function is, among other things, to prevent a silicide layer (not shown) often used for making ohmic contacts to source-drain regions 30, 28 from shorting out portion 271 of surface 27. Intermediately doped N-type region 29 is often provided extending from drain region 28 a short distance toward gate 36 to assist in controlling the electric field near drain region 28. Conductive contact 33 and terminal 331 are provided in ohmic contact with drain region 28. Conductive contact 39 with terminal 391 is provided in ohmic contact with source region 30 and P-well and substrate contact region 31. Gate terminal 363 is provided electrically coupled to gate 36.
5 to 10 volt LDMOS devices are widely used in wireless applications. 7.5 volt (and higher voltage) LDMOS devices are expected to be among the next generation of high frequency (>4 MHZ) power switches to replace the current generation 5 volt MOSFET devices that have potential reliability issues due to transient drain voltage overshoot at high frequencies. Shrinking LDMOS device sizes is a key requirement to obtain both high performance and lower cost. However, major design and process problems prevent current day LDMOS devices from being further shrunk below about 0.5 μm process technology. Breaking through the 0.5 μm barrier into 0.13 μm technology and below involves serious challenges, for example, misalignment errors, hot carrier injection (HCI) and leakage issues. Accordingly, there is an ongoing need to provide improved LDMOS devices structures and manufacturing processes that mitigate or avoid these and other problems encountered with current generation devices.
Accordingly, it is desirable to provide a new type of deep submicron semiconductor device, and more particularly, deep submicron LDMOS devices and methods able to operate at voltages above 5 volts. In addition, it is desirable to provide a structure and method for fabricating deep submicron LDMOS devices of improved performance below the current minimum channel length of 0.5 μm. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.